The present invention relates to a method of manufacturing a semiconductor device by which miniaturization of a wiring and enhancement of the degree of integration are facilitated while securing a voltage resistance between conductor layers used for wiring.
Attendant on the miniaturization of and enhancement of the degree of integration of semiconductor devices, the delay of electric signals due to the time constant of the wiring becomes a serious problem. For the conductor layers used in a multi-layer wiring step, the copper (Cu) wiring has come to be introduced in place of the wiring formed by use of an aluminum (Al) based alloy. Unlike the metallic materials used in the past for multi-layer wiring structures such as aluminum, copper is difficult to pattern by etching and, therefore, the so-called groove wiring technology (e.g., the Damascene process) is generally used in which wiring grooves are preliminarily formed between layers and are filled with copper to form a wiring pattern. Particularly, the methods in which connection holes and wiring grooves are preliminarily formed and both the holes and grooves are simultaneously filled with copper (e.g., the dual Damascene process) are effective for reducing the number of steps (see Japanese Patent Laid-open No. Hei 11-045887).
In addition, since an increase in the wiring capacity leads to a lowering in the operating speed of the device, a minute multi-layer wiring in which a low dielectric constant film is used as an interlayer insulation film is keenly needed. Examples of the material for the low dielectric constant interlayer insulation film include not only a fluorine-containing silicon oxide (FSG) having a dielectric constant of about 3.5 and having hitherto been used comparatively satisfactorily but also low dielectric constant films having a dielectric constant of about 2.7 such as organic silicon-based polymers represented by polyaryl ether (PAE) and inorganic materials represented by hydrogen silsesquioxane (HSQ) and methyl silsesquioxane (MSQ); in recent years, even the materials obtained by making these porous to attain a dielectric constant of about 2.2 have come to be introduced on trial.
In the case of applying the dual Damascene process to the low dielectric constant interlayer insulation film, it is desired for the process to overcome the following technical limitations.
First, since the composition of the low dielectric constant film is close to the composition of the resist used for patterning, the low dielectric constant film would also be liable to damage during the process of resist removal. Specifically, it is keenly desired that the resist peeling treatment after the etching by use of the resist mask and the resist regenerating treatment conducted when the treated resist pattern does not comply with the product specifications can be carried out without damaging the low dielectric constant film.
Next, problems might be generated in applying the process to a so-called borderless structure which lacks a margin in matching between the wiring and the connection hole. Attendant on the miniaturization of semiconductor devices, at least in the cases of multi-layer wirings of the 0.18 μm generation and the latter generations, it is a major premise that the machining process can cope with the borderless structure. Therefore, also in the case of simultaneous formation of wiring grooves and connection holes in an interlayer insulation film including a low dielectric constant film by the dual Damascene process, it is keenly desired that the process have little variations in via resistance due to misalignment.
In addition, in order to form the wiring grooves with good depth controllability, there may be need for the presence of an etching inhibitive film near the bottom portions of the wiring grooves. However, where the etching inhibitive film with a comparatively high dielectric constant is inserted as an intermediate layer, an increase in inter-layer capacity would result. Therefore, the dual Damascene process to be applied to the low dielectric constant film inter-layer structure may be required to be able to suppress the increase in capacity while controlling the formation of the wiring grooves.
Dual Damascene processes paying attention to the above-mentioned technical limitations have been disclosed (refer to, for example, Japanese Patent Laid-open Nos. 2000-150519 and 2001-44189). Besides, the present inventors have devised a dual Damascene process for a low dielectric constant film inter-layer structure including an organic film using a three-layer hard mask, as a dual Damascene process for a low dielectric film inter-layer structure capable of coping with high-performance devices of the 65 nm generation and the latter generations (refer to, for example, R. Kanamura et al, “Integration of Cu/low-k Dual-Damascene Interconnects with a Porous PAE/SiOC Hybrid Structure for 65 nm-node High Performance eDRAM”, 2003 Symposium on VSI Technology Digest of Technical Papers, pp. 107–108 (2003)).
According to the dual Damascene process devised by the present inventors, it is possible to easily form openings between connection hole layers composed of carbon-containing silicon oxide films while reducing the hard mask steps in resist patterning of connection holes, and it is possible to form dual Damascene wirings with good control of the wiring depth and the connection hole shape, even in the 100 nm half pitch minute multi-layer wiring of the 65 nm generation.
However, some technical barriers are present in the case where a next-generation multi-layer wiring for which further miniaturization and further lowering in dielectric constant are desired is formed by use of the dual Damascene process devised by the present inventors. The problems present in this case will be described referring FIGS. 9 and 10.
As shown in FIG. 9A, an interlayer insulation film 112 is formed on an under insulation film 111 deposited on a substrate (not shown). The interlayer insulation film 112 is formed, for example, by use of a laminate film composed of an organic film 113 and a silicon oxide (SiO2) film 114. The interlayer insulation film 112 is provided with a first wiring 116 by filling wiring grooves 115 with a copper (Cu) film through a close contact layer, a barrier meta layer or the like therebetween. In addition, an oxidation inhibitive layer 117 is formed on the first wiring 116 by use of a silicon carbide (SiC) film, for example.
Subsequently, a first insulation film 118 between connection hole layers is formed. As the first insulation film 118, a carbon-containing silicon oxide (SiOC) film was adopted. Next, a second insulation film 119 is formed on the first insulation film 118. As the second insulation film 119, a film of an organic polymer having a dielectric constant of about 2.6 is formed. In an embodiment, a polyaryl ether (PAE) film was formed as an example.
Subsequently, a first mask layer 131, a second mask layer 132, and a third mask layer 133 are sequentially formed on the second insulation film 119. Here, the first, second, and third mask layers 131, 132 and 133 are formed by use of a light-transmitting material; as an example, the first mask layer 131 was formed by use of a carbon-containing silicon oxide (SiOC) film, the second mask layer 132 was formed by use of a silicon nitride (SiN) film, and the third mask layer 133 was formed by use of a silicon oxide (SiO2) film. Thereafter, a resist mask 141 for formation of wiring grooves is formed on the third mask layer 133. The resist mask 141 is provided with opening portions 142 for formation of a wiring groove pattern.
Next, as shown in FIG. 9B, dry etching is conducted by use of the resist mask 141 [see FIG. 9A] as an etching mask, to form a wiring groove pattern 134 in the third mask layer 133. In addition, after the etching of the third mask layer 133, an ashing treatment based on an oxygen (O2) plasma and a treatment with an organic amine-based chemical, for example, are carried out, to completely remove the resist mask 141 and the residual deposits left upon the etching treatment.
Next, a resist mask 143 for formation of a connection hole pattern is formed. The resist mask 143 is provided with opening portions 144 for formation of connection holes. In addition, the resist mask 143 is so formed as to partly overlap with the wiring groove pattern 134 in the third mask layer 133. The resist mask 143 in relation to the formation of connection holes is so formed as to be aligned with the first wiring 116 or the wiring groove pattern 134; in this case, due to misalignment which may be generated on a lithography process basis and size dispersions of each layer, a region 122 constituting a borderless structure in relation to the wiring groove pattern 134 would be generated.
In the next place, as shown in FIG. 9C, by use of the resist mask 143 [see FIG. 9B] for connection hole pattern as an etching mask, a connection hole pattern 135 is formed in the third mask layer 133, the second mask layer 132, and the first mask layer 131 by a dry etching process. Further, connection holes 136 are formed in the second insulation film 119. Here, the resist mask 143 can be removed simultaneously by the etching treatment applied to the second insulation film 119 composed of the polyaryl ether film. In addition, the resist mask 143 gradually retreats into the openings in the second insulation film 119 composed of the polyaryl ether film, but the presence of the second mask 132 composed of the SiN film ensures that a good opening shape can be obtained.
Next, as shown in FIG. 9D, by use of the third mask 133 provided with the wiring groove pattern 134 as an etching mask, the wiring groove pattern 134 is extendedly formed in the SiN film of the second mask layer 132 by a dry etching process. In this case, upper portions of the first mask layer 131 are also etched. In addition, in the step of etching the second mask layer 132 by use of the third mask layer 133, the wiring groove pattern 134 can be extendedly formed through the second insulation film 119 composed of the organic film and exposed at bottom portions of the connection holes 136 to an intermediate portion of the first insulation film 118 composed of the SiOC film. Specifically, the etching selectivity ratio (SiN/SiOC) of the silicon nitride film of the second mask layer 132 to the SiOC film in this etching can be set to be less than 1 (one), and, therefore, in the case of etching the SiN film having a thickness of 50 nm, for example, it is possible to form the connection holes 136 in the SiOC film with a depth of about 80 nm inclusive of the required over-etching amount.
In the next place, as shown in FIG. 9E, the connection holes 136 are completely formed in the first insulation film 118 composed of the SiOC film. Here, the first mask layer 131 composed of the SiO2 film remaining in the wiring groove regions is simultaneously removed, by using as an etching mask the second mask layer 132 composed of the SiN film provided with the wiring groove pattern 134. It should be noted here that, during this etching step, carbon coming from the SiOC film of the first mask layer 131 is supplied in excess into the etching atmosphere in the wiring groove pattern 134 to be a large-width wiring, with the result that a stop of etching of the SiOC film would be liable to be generated. Therefore, the etching selectivity ratio (SiOC/SiN) relative to the SiN film under this etching condition is desired to set to a condition promising an enhancement of selective removal property, i.e., a ratio value of less than about 10, and the wiring groove pattern 134 formed in the SiOC film of the first mask 131 would have a shape emphasized in the so-called corner collapse. Besides, in the regions where the above-mentioned connection holes 136 and wiring groove pattern 134 have the borderless structure and where the adjacent wiring groove patterns 134 are laid out with a minimum space, the space between the wirings is narrowed, so that the corner collapse would tend to be further accelerated.
Thereafter, as shown in FIG. 9F, the polyaryl ether film of the second insulation film 119 remaining at bottom portions of the wiring groove pattern 134 is etched to form wiring grooves 137, and the SiC film of the oxidation inhibitive layer 117 present at bottom portions of the connection holes 136 is etched to further extend the connection holes 136. This results in that the connection holes 136 reach the first wiring 116. In this manner, the predetermined so-called dual Damascene processing is completed. The narrow space regions generated due to the misalignment in the connection hole patterning and the size dispersions mentioned above would not be broadened, through the spaces might be narrowed due to a further increase of the corner collapse. Incidentally, the SiN film of the second mask layer 131 left in the outside of the wiring groove regions is removed during the process of etching the SiC film of the oxidation inhibitive layer 117 at the bottom portions of the connection holes 136.
Next, by an after-treatment using an appropriate liquid chemical and a hydrogen annealing treatment, the etching deposits remaining on side walls of the wiring groove and the connection holes and the denatured Cu layer at bottom portions of the connection holes are cleaned up. Thereafter, as shown in FIG. 10A, a Ta film as a barrier metal layer 151, for example, is formed on the inside surfaces of the wiring grooves 137 and the connection holes 136 by a sputtering process, and, though not shown, a copper seed layer is formed and then a copper film 152 is deposited by an electroplating process, or the copper film 152 is deposited by a sputtering process. By this, the wiring grooves 137 and the connection holes 136 can be filled (buried) with a conductor film by use of copper. As the conductor film, other metallic materials than copper can also be used.
Further, of the copper film 152 and the barrier metal layer 151, the portions unnecessary for forming the second wiring are removed by a chemical mechanical polishing (CMP) process, whereby the second wiring 153 is completed in the wiring grooves 137, as shown in FIG. 10B, and parts thereof are connected to the first wiring 116 through the connection holes 136. By this a multi-layer wiring structure of the so-called dual Damascene structure is obtained. In addition, in the same manner as the first wiring 116 of the lower layer wiring, an oxidation inhibitive layer 154 for covering the second wiring 153 is formed by use of an SiC film, for example. However, at the narrow space portions generated due to the misalignment in the connection hole pattering and to the size dispersions mentioned above, regions 125 where the separation between the wiring is not satisfactory have been formed.
In relation to the multi-layer wiring formed by the dual Damascene process as above-mentioned, there has been confirmed a lowering in yield due to the shortcircuit defects between the wiring and the adjacent different-potential wiring, because of the generation of the regions 125 where the separation between the wirings are locally insufficient. Besides, it has been found that, even in the case where the different-potential wirings are separated within the range of operation of the semiconductor device, initial defects or wear faults due to an insufficient withstand voltage may be generated in cases of a separation width of 25 nm or less.
Prevention of the short-circuit defects and securing of the withstand voltage, in the wirings connected through the connection holes 136, have come to be serious problems in attendant on the progress of miniaturization.
A first one of the reasons is a reduction of the space between the wirings. For example, the space between the wirings is reduced to a minimum of 100 nm under the 65 nm generation design rule and to about 70 nm under the 45 nm generation design rule, and it is difficult in principle to improve the misalignment in the lithography process by an amount corresponding to the reduction of the space.
A second one of the reasons lies in that the degree of reduction in the opening size of the connection holes 136 is very high. In ordinary lithography processes, stable formation of the openings of the connection holes 136 becomes conspicuously difficult when the opening size becomes 120 nm or less. In addition, the degrees of difficulty in securing the wiring reliability concerning the subsequent filling-with-metal process, the reduction of resistance of the connection holes, stress migration, etc. are also raised. Therefore, the final opening size tends to remain on the greater side as compared with the reduction ratio of the inter-wiring space, which leads to a further difficulty in securing the required space between the wirings.
A third one of the reasons lies in that attendant on the miniaturization of wiring, the lowering of the dielectric constant of the insulation film is enlarged so as to reduce the capacity of the wiring, so that the withstand voltage of the film itself is lowered. Accordingly, the withstand voltage limit width tends rather to be enlarged, which again leads to a difficulty in securing the required space between the wirings.